As an example of a semiconductor memory device having a plurality of types of memories integrated in one chip, there is a OneNAND (a registered trademark) (see, e.g., JP-A 2006-286179 (KOKAI)). In this OneNAND, a NAND flash memory as a main memory unit, an SRAM as a buffer unit and others are integrated in one chip. Further, in the OneNAND, a controller having a state machine mounted thereon is prepared to control data transfer between, e.g., a NAND flash memory and an SRAM.
Here, in the OneNAND, the SRAM can be formed of a plurality of buffer memories having different bank structures.
However, when controlling operations in the plurality of buffer memories by using the same timer, a synchronous operation is also set in accordance with an asynchronous operation in conventional examples. In this case, to cope with skew of an external input signal input from the outside at the time of the asynchronous operation, a longer operation period is set. Therefore, in the synchronous operation, the operation period that is long beyond necessity is set.
That is, when a plurality of memory devices having different configurations are present in one chip, a control timer must be coordinated with the slowest memory device in each operation to guarantee data. Therefore, there is a problem that the coordination with the slowest memory device must be carried out even in the synchronous operation and hence a speed of the operation cannot be increased.